Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810510 | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout | Julie Segal | 2004-10-26 |
| 6795953 | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design | Julie Segal | 2004-09-21 |