Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810510 | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout | Sergei G. Bakarian | 2004-10-26 |
| 6795953 | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design | Sergei G. Bakarian | 2004-09-21 |
| 6780656 | Correction of overlay offset between inspection layers | David J. Muradian, John Caywood, Brian Duffy | 2004-08-24 |
| 6745370 | Method for selecting an optimal level of redundancy in the design of memories | David Lepejian, John Caywood | 2004-06-01 |
| 6701477 | Method for identifying the cause of yield loss in integrated circuit manufacture | — | 2004-03-02 |