Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825084 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoya Saito, Kimihiro Satoh | 2004-11-30 |
| 6807105 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2004-10-19 |
| 6759290 | Stitch and select implementation in twin MONOS array | Tomoya Saito, Seiki Ogura, Kimihiro Satoh | 2004-07-06 |
| 6714456 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2004-03-30 |
| 6686632 | Dual-bit multi-level ballistic MONOS memory | Seiki Ogura, Yutaka Hayashi | 2004-02-03 |