Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825544 | Method for shallow trench isolation and shallow trench isolation structure | — | 2004-11-30 |
| 6808944 | Structure and method for monitoring a semiconductor process, and method of making such a structure | Kaichiu Wong | 2004-10-26 |
| 6800495 | Lot-optimized wafer level burn-in | Cesar Payan | 2004-10-05 |
| 6759865 | Array of dice for testing integrated circuits | Qi Gu | 2004-07-06 |
| 6734108 | Semiconductor structure and method of making contacts in a semiconductor structure | Jianmin Qiao, Shahin Sharifzadeh | 2004-05-11 |