AM

Anmol Mathur

CS Cadence Design Systems: 4 patents #4 of 106Top 4%
📍 San Jose, CA: #161 of 2,805 inventorsTop 6%
🗺 California: #1,346 of 28,370 inventorsTop 5%
Overall (2004): #17,002 of 270,089Top 7%
4
Patents 2004

Issued Patents 2004

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
6832357 Reducing datapath widths by rebalancing data flow topology Sanjeev Saluja 2004-12-14
6807651 Procedure for optimizing mergeability and datapath widths of data flow graphs Sanjeev Saluja 2004-10-19
6772398 Reducing datapath widths responsively to upper bound on information content Sanjeev Saluja 2004-08-03
6772399 Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision Sanjeev Saluja 2004-08-03