Issued Patents 2004
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6829757 | Method and apparatus for generating multi-layer routes | Andrew Caldwell | 2004-12-07 |
| 6826737 | Recursive partitioning placement method and apparatus | Joseph L. Ganley | 2004-11-30 |
| 6802049 | Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies | Joseph L. Ganley | 2004-10-05 |
| 6795958 | Method and apparatus for generating routes for groups of related node configurations | Joseph L. Ganley | 2004-09-21 |
| 6769105 | Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits | Andrew Caldwell | 2004-07-27 |
| 6745379 | Method and apparatus for identifying propagation for routes with diagonal edges | Oscar Buset | 2004-06-01 |
| 6738960 | Method and apparatus for producing sub-optimal routes for a net by generating fake configurations | Oscar Buset, Yang Lin | 2004-05-18 |
| 6735748 | Method and apparatus for performing extraction using a model trained with bayesian inference | Arindam Chatterjee | 2004-05-11 |
| 6711727 | Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits | Andrew Caldwell | 2004-03-23 |
| 6701306 | Methods and apparatus for manipulating polygons in a multidimensional space | Tom Kronmiller | 2004-03-02 |
| 6687893 | Method and apparatus for pre-computing routes for multiple wiring models | Joseph L. Ganley | 2004-02-03 |
| 6687887 | Method and apparatus for performing extraction using a model trained with Bayesian inference using a hybrid monte carlo method | Arindam Chatterjee | 2004-02-03 |
| 6678872 | Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout | Joseph L. Ganley | 2004-01-13 |