JG

Joseph L. Ganley

CS Cadence Design Systems: 5 patents #2 of 106Top 2%
📍 Herndon, VA: #1 of 40 inventorsTop 3%
🗺 Virginia: #28 of 1,885 inventorsTop 2%
Overall (2004): #8,831 of 270,089Top 4%
5
Patents 2004

Issued Patents 2004

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
6826737 Recursive partitioning placement method and apparatus Steven Teig 2004-11-30
6802049 Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies Steven Teig 2004-10-05
6795958 Method and apparatus for generating routes for groups of related node configurations Steven Teig 2004-09-21
6687893 Method and apparatus for pre-computing routes for multiple wiring models Steven Teig 2004-02-03
6678872 Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout Steven Teig 2004-01-13