Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6818491 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong | 2004-11-16 |
| 6788612 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-09-07 |
| 6788611 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-09-07 |
| 6777292 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong | 2004-08-17 |
| 6757196 | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | Hsing-Ya Tsao, Fu-Chang Hsu | 2004-06-29 |
| 6717846 | Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration | Hung-Sheng Chen, Vei-Han Chan | 2004-04-06 |
| 6714457 | Parallel channel programming scheme for MLC flash memory | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-03-30 |
| 6687154 | Highly-integrated flash memory and mask ROM array architecture | Fu-Chang Hsu | 2004-02-03 |
| 6680859 | Logic process DRAM | Winston Lee, Sehat Sutardja | 2004-01-20 |