JY

Jeongsik Yang

IL Integrated Memory Logic: 1 patents #1 of 7Top 15%
📍 San Jose, CA: #929 of 2,756 inventorsTop 35%
🗺 California: #8,996 of 28,521 inventorsTop 35%
Overall (2003): #197,362 of 273,478Top 75%
1
Patents 2003

Issued Patents 2003

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6647506 Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle Young Gon Kim, Chiayao S. Tung, Shuen-Chin Chang, Yong-Eun Park 2003-11-11