BD

Bulent Dervisoglu

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
IN Intel: 1 patents #759 of 2,151Top 40%
📍 Framingham, MA: #18 of 100 inventorsTop 20%
🗺 Massachusetts: #830 of 6,881 inventorsTop 15%
Overall (2003): #73,830 of 273,478Top 30%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6631504 Hierarchical test circuit structure for chips with multiple circuit blocks Laurence H. Cooke 2003-10-07
6594802 Method and apparatus for providing optimized access to circuits for debug, programming, and test Michael Ricchetti, Christopher J. Clark 2003-07-15