Issued Patents 2003
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664639 | Contact and via structure and method of fabrication | — | 2003-12-16 |
| 6649451 | Structure and method for wafer comprising dielectric and semiconductor | Michael A. Vyvoda, Calvin K. Li, Samuel V. Dunton | 2003-11-18 |
| 6639312 | Dummy wafers and methods for making the same | Scott Brad Herner | 2003-10-28 |
| 6635556 | Method of preventing autodoping | Scott Brad Herner, Johan Knall | 2003-10-21 |
| 6627530 | Patterning three dimensional structures | Calvin K. Li, N. Johan Knall, Michael A. Vyvoda, Vivek Subramanian | 2003-09-30 |
| 6624011 | Thermal processing for three dimensional circuits | Vivek Subramanian, N. Johan Knall, Calvin K. Li, Michael A. Vyvoda | 2003-09-23 |
| 6591394 | Three-dimensional memory array and method for storing data bits and ECC bits therein | Thomas H. Lee, Mark G. Johnson | 2003-07-08 |
| 6580124 | Multigate semiconductor device with vertical channel current and method of fabrication | Vivek Subramanian | 2003-06-17 |
| 6574145 | Memory device and method for sensing while programming a non-volatile memory cell | Bendik Kleveland, Roy E. Scheuerlein | 2003-06-03 |
| 6541312 | Formation of antifuse structure in a three dimensional memory | Michael A. Vyvoda, N. Johan Knall | 2003-04-01 |
| 6534403 | Method of making a contact and via structure | — | 2003-03-18 |
| 6515904 | Method and system for increasing programming bandwidth in a non-volatile memory device | Christopher S. Moore, Bendik Kleveland, Roger March, Roy E. Scheuerlein | 2003-02-04 |
| 6515923 | Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays | — | 2003-02-04 |