Issued Patents 2003
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6562638 | Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout | Artur P. Balasinski, Robert C. Pack, Victor Boksha | 2003-05-13 |
VA
Valery Axelrad
Cadence Design Systems: 1 patents #17 of 82Top 25%
Overall (2003): #97,284 of 273,478Top 40%
1
Patents 2003