VB

Victor Boksha

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
Cypress Semiconductor: 1 patents #56 of 221Top 30%
📍 Los Altos, CA: #179 of 436 inventorsTop 45%
🗺 California: #8,996 of 28,521 inventorsTop 35%
Overall (2003): #96,673 of 273,478Top 40%
1
Patents 2003

Issued Patents 2003

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6562638 Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout Artur P. Balasinski, Robert C. Pack, Valery Axelrad 2003-05-13