YU

Yuso Udo

KT Kabushiki Kaisha Toshiba: 2 patents #287 of 1,928Top 15%
📍 Chofu, JP: #6 of 40 inventorsTop 15%
Overall (2003): #34,547 of 273,478Top 15%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6630714 Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer Tsutomu Sato, Hajime Nagano, Ichiro Mizushima, Takashi Yamada, Shinichi Nitta 2003-10-07
6515733 Pattern exposure apparatus for transferring circuit pattern on semiconductor wafer and pattern exposure method 2003-02-04