Issued Patents 2003
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6661706 | Semiconductor storage device having page copying | Koichi Kawai, Hiroshi Nakamura | 2003-12-09 |
| 6657896 | Fail number detecting circuit of flash memory | Koji Hosono, Tamio Ikehashi, Tomoharu Tanaka, Hiroshi Nakamura, Ken Takeuchi | 2003-12-02 |
| 6649945 | Wiring layout to weaken an electric field generated between the lines exposed to a high voltage | Koji Hosono, Hiroshi Nakamura | 2003-11-18 |
| 6642775 | Potential detector and semiconductor integrated circuit | — | 2003-11-04 |
| 6621735 | Semiconductor memory device using only single-channel transistor to apply voltage to selected word line | Hiroshi Nakamura | 2003-09-16 |
| 6611447 | Semiconductor memory device capable of realizing a chip with high operation reliability and high yield | Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kazuhito Narita, Kazuhiro Shimizu +1 more | 2003-08-26 |
| 6597602 | Semiconductor memory device | Hiroshi Nakamura, Koji Hosono | 2003-07-22 |
| 6590444 | Semiconductor integrated circuit with a down converter for generating an internal voltage | Tamio Ikehashi, Yoshihisa Sugiura, Ken Takeuchi, Yoshihisa Iwata | 2003-07-08 |
| 6522583 | Nonvolatile semiconductor memory | Kazushige Kanda, Hiroshi Nakamura, Koji Hosono, Tamio Ikehashi | 2003-02-18 |
| 6512253 | Nonvolatile semiconductor memory | Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi +3 more | 2003-01-28 |
| 6507508 | Pattern layout of transfer transistors employed in row decoder | Koji Hosono, Hiroshi Nakamura, Tomoharu Tanaka | 2003-01-14 |
| 6507518 | Fail number detecting circuit of flash memory | Koji Hosono, Tamio Ikehashi, Tomoharu Tanaka, Hiroshi Nakamura, Ken Takeuchi | 2003-01-14 |