Issued Patents 2003
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6567959 | Method and device for verification of VLSI designs | Alexander Levin, Carl Seger | 2003-05-20 |
| 6564358 | Method and system for formal verification of a circuit model using binary decision diagrams | John Moondanos, Carl Seger, Daher Kaiss | 2003-05-13 |