Issued Patents 2003
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6567959 | Method and device for verification of VLSI designs | Alexander Levin, Ziyad Hanna | 2003-05-20 |
| 6564358 | Method and system for formal verification of a circuit model using binary decision diagrams | John Moondanos, Ziyad Hanna, Daher Kaiss | 2003-05-13 |
| 6539345 | Symbolic simulation using input space decomposition via Boolean functional representation in parametric form | Robert B. Jones | 2003-03-25 |