TS

Tsengyou Syau

IT Integrated Device Technology: 2 patents #5 of 36Top 15%
📍 Portland, OR: #124 of 740 inventorsTop 20%
🗺 Oregon: #337 of 2,269 inventorsTop 15%
Overall (2003): #38,105 of 273,478Top 15%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6566236 Gate structures with increased etch margin for self-aligned contact and the method of forming the same Guo-Qiang Lo, Shih-Ked Lee, Chuen-Der Lien, Sang-Yun Lee, Ching-Kai Lin 2003-05-20
6534414 Dual-mask etch of dual-poly gate in CMOS processing Kuilong Wang, Shih-Ked Lee, Chuen-Der Lien 2003-03-18