Issued Patents 2003
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6571374 | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips | Robert T. Sayah, Joseph Roland Verock, Steven E. Washburn | 2003-05-27 |
| 6567958 | Invention to allow hierarchical logical-to-physical checking on chips | Joseph Roland Verock | 2003-05-20 |
| 6507930 | Method and system for improving yield of semiconductor integrated circuits | Roy Bass | 2003-01-14 |