Issued Patents 2003
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651230 | Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design | John M. Cohn, Jose L. Neves | 2003-11-18 |
| 6543040 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Scott Whitney Gould, Jeannie H. Panner | 2003-04-01 |
| 6523154 | Method for supply voltage drop analysis during placement phase of chip design | John M. Cohn, James Venuto, Ivan L. Wemple | 2003-02-18 |
| 6505324 | Automated fuse blow software system | Bruce Cowan, Frank Distler, Mark F. Ollive, Michael R. Ouellette, Jeannie H. Panner +2 more | 2003-01-07 |