Issued Patents 2003
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651230 | Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design | Jose L. Neves, Paul S. Zuchowski | 2003-11-18 |
| 6574779 | Hierarchical layout method for integrated circuits | Robert J. Allen, Steve Lovejoy | 2003-06-03 |
| 6523154 | Method for supply voltage drop analysis during placement phase of chip design | James Venuto, Ivan L. Wemple, Paul S. Zuchowski | 2003-02-18 |
| 6523159 | Method for adding decoupling capacitance during integrated circuit design | Kerry Bernstein, Jose L. Neves | 2003-02-18 |