Issued Patents 2003
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670240 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoya Saito, Kimihiro Satoh | 2003-12-30 |
| 6643172 | Bit line decoding scheme and circuit for dual bit memory with a dual bit selection | — | 2003-11-04 |
| 6636439 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-10-21 |
| 6636438 | Control gate decoder for twin MONOS memory with two bit erase capability | Nori Ogura | 2003-10-21 |
| 6631089 | Bit line decoding scheme and circuit for dual bit memory array | Nori Ogura | 2003-10-07 |
| 6631088 | Twin MONOS array metal bit organization and single cell operation | Seiki Ogura, Tomoya Saito | 2003-10-07 |
| 6628547 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-09-30 |
| 6628546 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-09-30 |
| 6611461 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-08-26 |
| 6567314 | Data programming implementation for high efficiency CHE injection | Seiki Ogura | 2003-05-20 |
| 6549463 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-04-15 |
| 6542412 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2003-04-01 |
| 6535430 | Wordline decoder for flash memory | Masaharu Kirihara | 2003-03-18 |