Issued Patents 2003
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670240 | Twin NAND device structure, array operations and fabrication method | Tomoko Ogura, Tomoya Saito, Kimihiro Satoh | 2003-12-30 |
| 6642572 | Nonvolatile semiconductor memory device and method for fabricating the same | Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka | 2003-11-04 |
| 6636439 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-10-21 |
| 6631088 | Twin MONOS array metal bit organization and single cell operation | Tomoya Saito, Tomoko Ogura | 2003-10-07 |
| 6628547 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-09-30 |
| 6628546 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-09-30 |
| 6611461 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-08-26 |
| 6580116 | Double sidewall short channel split gate flash memory | — | 2003-06-17 |
| 6567314 | Data programming implementation for high efficiency CHE injection | Tomoko Ogura | 2003-05-20 |
| 6558997 | Method for fabricating the control and floating gate electrodes without having their upper surface silicided | Fumihiko Noro | 2003-05-06 |
| 6549463 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-04-15 |
| 6545312 | Nonvolatile semiconductor memory device and method for fabricating the same | Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka | 2003-04-08 |
| 6542412 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Tomoko Ogura | 2003-04-01 |
| 6538275 | Nonvolatile semiconductor memory device and method for fabricating the same | Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka | 2003-03-25 |
| 6531350 | Twin MONOS cell fabrication method and array organization | Kimihiro Satoh, Tomoya Saito | 2003-03-11 |