JC

James Chieh-Tsung Chen

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
TSMC: 1 patents #218 of 754Top 30%
📍 Foster City, CA: #20 of 111 inventorsTop 20%
🗺 California: #4,287 of 28,521 inventorsTop 20%
Overall (2003): #62,860 of 273,478Top 25%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6560755 Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits Xisheng Zhang, Zhihong Liu, Jushan Xie, Xucheng Pang, Jingkun Fang 2003-05-06
6534396 Patterned conductor layer pasivation method with dimensionally stabilized planarization Fu-Jier Fahn, Kuo-Wei Lin, Eugene Cheu, Chien-Shian Peng, Gilbert Fan +1 more 2003-03-18