ST

Steven Teig

CS Cadence Design Systems: 7 patents #1 of 82Top 2%
📍 Menlo Park, CA: #8 of 354 inventorsTop 3%
🗺 California: #452 of 28,521 inventorsTop 2%
Overall (2003): #3,624 of 273,478Top 2%
7
Patents 2003

Issued Patents 2003

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
6671864 Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net Joseph L. Ganley 2003-12-30
6651233 Method and apparatus for measuring congestion in a partitioned region Joseph L. Ganley 2003-11-18
6625611 Method and apparatus for representing multidimensional data Tom Kronmiller, Andrew Siegel 2003-09-23
6618849 Method and apparatus for identifying routes for nets Heng-Yi Chao 2003-09-09
6581198 Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring Arindam Chatterjee 2003-06-17
6526555 Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction Andrew Caldwell 2003-02-25
6516455 Partitioning placement method using diagonal cutlines Joseph L. Ganley 2003-02-04