AC

Arindam Chatterjee

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
📍 Saratoga, CA: #156 of 341 inventorsTop 50%
🗺 California: #8,996 of 28,521 inventorsTop 35%
Overall (2003): #261,104 of 273,478Top 100%
1
Patents 2003

Issued Patents 2003

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6581198 Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring Steven Teig 2003-06-17