Issued Patents 2003
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6621325 | Structures and methods for selectively applying a well bias to portions of a programmable device | Michael J. Hart, Daniel Gitlin, Hua Shen, Stephen M. Trimberger | 2003-09-16 |
| 6621296 | FPGA lookup table with high speed read decorder | Richard A. Carberry, Trevor J. Bauer | 2003-09-16 |
| 6612546 | Gate valve with delayed retraction of counter plate | Vaclav Myslivec | 2003-09-02 |
| 6603332 | Configurable logic block for PLD with logic gate for combining output with another configurable logic block | Alireza S. Kaviani, Sundararajarao Mohan, Ralph D. Wittig, Bernard J. New | 2003-08-05 |
| 6573749 | Method and apparatus for incorporating a multiplier into an FPGA | Bernard J. New | 2003-06-03 |
| 6529040 | FPGA lookup table with speed read decoder | Richard A. Carberry, Trevor J. Bauer | 2003-03-04 |
| 6526557 | Architecture and method for partially reconfiguring an FPGA | Trevor J. Bauer | 2003-02-25 |
| 6525565 | Double data rate flip-flop | Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2003-02-25 |
| 6522167 | User configurable on-chip memory system | Ahmad R. Ansari, Stephen M. Douglass, Mehul R. Vashi | 2003-02-18 |