Issued Patents 2002
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6498058 | SOI pass-gate disturb solution | Andres Bryant, Edward J. Nowak | 2002-12-24 |
| 6475838 | Methods for forming decoupling capacitors | Andres Bryant, William F. Clark, Jr., Edward J. Nowak | 2002-11-05 |
| 6469350 | Active well schemes for SOI technology | William F. Clark, Jr., Edward J. Nowak, Jed H. Rankin | 2002-10-22 |
| 6459106 | Dynamic threshold voltage devices with low gate to substrate resistance | Andres Bryant, Edward J. Nowak | 2002-10-01 |
| 6455766 | Contact-less probe of semiconductor wafers | Donald J. Cook, Edward J. Nowak | 2002-09-24 |
| 6437594 | SOI pass gate leakage monitor | Ronald J. Bolam, Andres Bryant, Edward J. Nowak | 2002-08-20 |
| 6436744 | Method and structure for creating high density buried contact for use with SOI processes for high performance logic | Andres Bryant, Jerome B. Lasky, Edward J. Nowak, Jed H. Rankin | 2002-08-20 |
| 6429056 | Dynamic threshold voltage devices with low gate to substrate resistance | Andres Bryant, Edward J. Nowak | 2002-08-06 |
| 6424174 | Low leakage logic gates | Edward J. Nowak | 2002-07-23 |
| 6404236 | Domino logic circuit having multiplicity of gate dielectric thicknesses | Kerry Bernstein, Andres Bryant, Robert J. Gauthier, Jr., Edward J. Nowak | 2002-06-11 |
| 6400171 | Method and system for processing integrated circuits | Andres Bryant, William D. K. Clark, Edward J. Nowak | 2002-06-04 |
| 6365484 | Method of forming semiconductor device with decoupling capacitance | Edward J. Nowak | 2002-04-02 |