Issued Patents 2002
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6418514 | Removal of posted operations from cache operations queue | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-07-09 |
| 6418516 | Method and system for managing speculative requests in a multi-level memory hierarchy | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, William J. Starke | 2002-07-09 |
| 6415358 | Cache coherency protocol having an imprecise hovering (H) state for instructions and data | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-07-02 |
| 6405285 | Layered local cache mechanism with split register load bus and cache load bus | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-06-11 |
| 6397298 | Cache memory having a programmable cache replacement scheme | Ravi Kumar Arimilli, Guy L. Guthrie | 2002-05-28 |
| 6397320 | Method for just-in-time delivery of load data via cycle of dependency | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-05-28 |
| 6397300 | High performance store instruction management via imprecise local cache update mechanism | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-05-28 |
| 6393528 | Optimized cache allocation algorithm for multiple speculative requests | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-05-21 |
| 6393553 | Acknowledgement mechanism for just-in-time delivery of load data | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-05-21 |
| 6389529 | Method for alternate preferred time delivery of load data | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-05-14 |
| 6385702 | High performance multiprocessor system with exclusive-deallocate cache state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-05-07 |
| 6385694 | High performance load instruction management via system bus with explicit register load and/or cache reload protocols | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-05-07 |
| 6374333 | Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-04-16 |
| 6374330 | Cache-coherency protocol with upstream undefined state | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-04-16 |
| 6360299 | Extended cache state with prefetched stream ID information | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-03-19 |
| 6353875 | Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-03-05 |
| 6349369 | Protocol for transferring modified-unsolicited state during data intervention | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-02-19 |
| 6349367 | Method and system for communication in which a castout operation is cancelled in response to snoop responses | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-02-19 |
| 6347361 | Cache coherency protocols with posted operations | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-02-12 |
| 6347363 | Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-02-12 |
| 6345340 | Cache coherency protocol with ambiguous state for posted operations | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-02-05 |
| 6345344 | Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-02-05 |
| 6345343 | Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-02-05 |
| 6345342 | Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2002-02-05 |
| 6345339 | Pseudo precise I-cache inclusivity for vertical caches | Ravi Kumar Arimilli | 2002-02-05 |