Issued Patents 2002
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6440816 | Alignment mark fabrication process to limit accumulation of errors in level to level overlay | Reginald Conway Farrow | 2002-08-27 |
| 6383879 | Semiconductor device having a metal gate with a work function compatible with a semiconductor device | Ranbir Singh, Lori Stirling | 2002-05-07 |
| 6380606 | Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same | David C. Brady, Pradip K. Roy, Hem M. Vaidya | 2002-04-30 |
| 6365511 | Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability | Sailesh Mansinh Merchant, Joseph R. Radosevich | 2002-04-02 |
| 6359339 | Multi-layered metal silicide resistor for Si Ic's | Richard W. Gregor, Sailesh Mansinh Merchant, Jaseph R. Radosevich, Pradip K. Roy | 2002-03-19 |
| 6339246 | Tungsten silicide nitride as an electrode for tantalum pentoxide devices | Sailesh Mansinh Merchant, Pradip K. Roy | 2002-01-15 |
| 6335557 | Metal silicide as a barrier for MOM capacitors in CMOS technologies | Sailesh Mansinh Merchant, Joseph R. Radosevich | 2002-01-01 |