LE

Lawrence B. Edwards

VT Vlsi Technology: 3 patents #2 of 143Top 2%
📍 San Jose, CA: #82 of 1,308 inventorsTop 7%
🗺 California: #921 of 17,285 inventorsTop 6%
Overall (1997): #13,804 of 185,788Top 8%
3
Patents 1997

Issued Patents 1997

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
5689433 Method and apparatus for compacting integrated circuits with wire length minimization 1997-11-18
5625568 Method and apparatus for compacting integrated circuits with standard cell architectures Andy T. Ngo 1997-04-29
5612893 Method and apparatus for compacting integrataed circuits with transistor sizing Ling Hao 1997-03-18