Issued Patents 1997
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5692197 | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Charles E. Narad, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Louis F. Coffin, III +1 more | 1997-11-25 |
| 5689713 | Method and apparatus for interrupt communication in a packet-switched computer system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo, Sun Den Chen, Charles E. Narad | 1997-11-18 |
| 5684977 | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | William C. Van Loo, Satyanarayana Nishtala, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-11-04 |
| 5657472 | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | William C. Van Loo, Satyanarayana Nishtala, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III +1 more | 1997-08-12 |
| 5655100 | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Paul N. Loewenstein, Louis F. Coffin, III | 1997-08-05 |
| 5644753 | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Kevin Normoyle, Satyanarayana Nishtala, William C. Van Loo | 1997-07-01 |
| 5634068 | Packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Leslie D. Kohn, Louis F. Coffin, III | 1997-05-27 |