KD

Kathakali Debnath

IN Intel: 2 patents #88 of 703Top 15%
📍 Beaverton, OR: #22 of 200 inventorsTop 15%
🗺 Oregon: #142 of 1,309 inventorsTop 15%
Overall (1997): #34,399 of 185,788Top 20%
2
Patents 1997

Issued Patents 1997

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5666537 Power down scheme for idle processor components Anurag Sah, Cong Q. Khieu 1997-09-09
5630107 System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy Douglas M. Carmean, Roshan Fernando, Robert F. Krick, Keng L. Wong 1997-05-13