JC

Jeffrey D. Currin

CS Credence Systems: 1 patents #3 of 5Top 60%
📍 Pleasanton, CA: #41 of 151 inventorsTop 30%
🗺 California: #4,598 of 17,285 inventorsTop 30%
Overall (1997): #133,188 of 185,788Top 75%
1
Patents 1997

Issued Patents 1997

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
5684421 Compensated delay locked loop timing vernier Douglas J. Chapman 1997-11-04