Issued Patents 1997
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5689672 | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions | Michael D. Goddard | 1997-11-18 |
| 5684422 | Pipelined microprocessor including a high speed single-clock latch circuit | Marty Pflum | 1997-11-04 |
| 5664136 | High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations | William M. Johnson | 1997-09-02 |
| 5655097 | High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format | William M. Johnson | 1997-08-05 |
| 5655098 | High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format | William M. Johnson | 1997-08-05 |
| 5651125 | High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations | William M. Johnson | 1997-07-22 |
| 5630100 | Simulating multi-phase clock designs using a single clock edge based system | Gopi Ganapathy | 1997-05-13 |
| 5623627 | Computer memory architecture including a replacement cache | — | 1997-04-22 |
| 5623619 | Linearly addressable microprocessor cache | — | 1997-04-22 |