DT

Danesh Tavana

AM AMD: 2 patents #88 of 389Top 25%
📍 San Jose, CA: #163 of 1,308 inventorsTop 15%
🗺 California: #1,869 of 17,285 inventorsTop 15%
Overall (1997): #42,584 of 185,788Top 25%
2
Patents 1997

Issued Patents 1997

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5682107 FPGA architecture with repeatable tiles including routing matrices and logic matrices Wilson K. Yee, Victor A. Holen 1997-10-28
5635851 Read and writable data bus particularly for programmable logic devices 1997-06-03