Issued Patents 1994
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5371031 | Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions | Inn K. Lee | 1994-12-06 |
| 5365082 | MOSFET cell array | Pradeep L. Shah, Dave J. McElroy | 1994-11-15 |
| 5354703 | EEPROM cell array with tight erase distribution | — | 1994-10-11 |
| 5350706 | CMOS memory cell array | Dave J. McElroy, Pradeep L. Shah | 1994-09-27 |
| 5340768 | Method of fabricating self-aligned field-plate isolation between control electrodes | — | 1994-08-23 |
| 5334550 | Method of producing a self-aligned window at recessed intersection of insulating regions | David J. McElroy, Sung-Wei Lin | 1994-08-02 |
| 5321288 | Nonvolatile memory array in which each cell has a single floating gate having two tunnelling windows | Theodore D. Lindgren | 1994-06-14 |
| 5313432 | Segmented, multiple-decoder memory array and method for programming a memory array | Sung-Wei Lin, John F. Schreck, Phat C. Truong, David J. McElroy, Harvey J. Stiegler +1 more | 1994-05-17 |
| 5306658 | Method of making virtual ground memory cell array | — | 1994-04-26 |
| 5284785 | Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and methods for making and using the same | — | 1994-02-08 |
| 5283203 | Self-aligned contact process for complementary field-effect integrated circuits | Danny Pak-Chum Shum | 1994-02-01 |