DP

Dipankar Pramanik

VT Vlsi Technology: 3 patents #11 of 95Top 15%
📍 Saratoga, CA: #9 of 169 inventorsTop 6%
🗺 California: #488 of 13,957 inventorsTop 4%
Overall (1994): #13,867 of 165,921Top 9%
3
Patents 1994

Issued Patents 1994

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
5374833 Structure for suppression of field inversion caused by charge build-up in the dielectric Subhash R. Nariani, Vivek Jain, Kuang-Yeh Chang 1994-12-20
5332868 Method and structure for suppressing stress-induced defects in integrated circuit conductive lines Vivek Jain 1994-07-26
5290727 Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors Vivek Jain, Subhash R. Nariani 1994-03-01