Issued Patents 1994
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5377336 | Improved method to prefetch load instruction data | Richard J. Eickemeyer | 1994-12-27 |
| 5359718 | Early scalable instruction set machine alu status prediction apparatus | James E. Phillips | 1994-10-25 |
| 5355460 | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution | Richard J. Eickemeyer, Bartholomew Blaner | 1994-10-11 |
| 5337395 | SPIN: a sequential pipeline neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-08-09 |
| 5329611 | Scalable flow virtual learning neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-07-12 |
| 5325464 | Pyramid learning architecture neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-06-28 |
| 5303356 | System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag | Bartholomew Blaner, Thomas L. Jeremiah | 1994-04-12 |
| 5303176 | High performance array multiplier using four-to-two composite counters | David A. Hrusecky, James E. Phillips | 1994-04-12 |
| 5301341 | Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions | James E. Phillips | 1994-04-05 |
| 5299319 | High performance interlock collapsing SCISM ALU apparatus | James E. Phillips | 1994-03-29 |
| 5295249 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel | Bartholomew Blaner | 1994-03-15 |
| 5287467 | Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit | Bartholomew Blaner, Thomas L. Jeremiah, Phillip G. Williams | 1994-02-15 |