Issued Patents 1994
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5377146 | Hierarchical redundancy scheme for high density monolithic memories | Chitranjan N. Reddy | 1994-12-27 |
| 5375097 | Segmented bus architecture for improving speed in integrated circuit memories | Chitranjan N. Reddy | 1994-12-20 |
| 5306958 | High-speed address transition detection circuit | Chitranjan N. Reddy | 1994-04-26 |