Issued Patents 1989
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4890011 | On-chip substrate bias generating circuit having substrate potential clamp and operating method therefor | — | 1989-12-26 |
| 4843596 | Semiconductor memory device with address transition detection and timing control | Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-06-27 |
| 4837747 | Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block | Katsumi Dosaka, Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi, Hiroyuki Yamasaki +3 more | 1989-06-06 |
| 4823322 | Dynamic random access memory device having an improved timing arrangement | Masaki Kumanoya, Hideto Hidaka, Yasuhiro Konishi, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-04-18 |
| 4811304 | MDS decoder circuit with high voltage suppression of a decoupling transistor | Yoshio Matsuda, Kazuyasu Fujishima | 1989-03-07 |
| 4809230 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideto Hidaka, Katsumi Dosaka | 1989-02-28 |