Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853244 | Reconfigurable computer accelerator providing stream processor and dataflow processor | Anthony Nowatzki, Vinay Gangadhar | 2023-12-26 |
| 11513805 | Computer architecture with synergistic heterogeneous processors | Anthony Nowatzki | 2022-11-29 |
| 11151077 | Computer architecture with fixed program dataflow elements and stream processor | Anthony Nowatzki, Vinay Gangadhar | 2021-10-19 |
| 11048661 | Systems and methods for stream-dataflow acceleration wherein a delay is implemented so as to equalize arrival times of data packets at a destination functional unit | Anthony Nowatzki, Vinay Gangadhar, Preyas Shah, Newsha Ardalani | 2021-06-29 |
| 11042797 | Accelerating parallel processing of data in a recurrent neural network | Yunfeng Li, Vinay Gangadhar, Anthony Nowatzki | 2021-06-22 |
| 10963384 | Method, computer program product, and apparatus for acceleration of simultaneous access to shared data | Vinay Gangadhar, Anthony Nowatzki, Yunfeng Li | 2021-03-30 |
| 10936536 | Memory processing core architecture | Jaikrishnan Menon, Lorenzo De Carli | 2021-03-02 |
| 10754744 | Method of estimating program speed-up in highly parallel architectures using static analysis | Newsha Ardalani, Urmish Ajit Thakker | 2020-08-25 |
| 10591983 | Computer accelerator system using a trigger architecture memory access processor | Chen-Han Ho, Sung Kim | 2020-03-17 |
| 10289604 | Memory processing core architecture | Jaikrishnan Menon, Lorenzo De Carli | 2019-05-14 |
| 10216693 | Computer with hybrid Von-Neumann/dataflow execution architecture | Anthony Nowatzki, Vinay Gangadhar | 2019-02-26 |
| 9619233 | Computer processor providing exception handling with reduced state storage | Jaikrishnan Menon, Marc Asher De Kruijf | 2017-04-11 |
| 9500705 | Integrated circuit providing fault prediction | Raghuraman Balasubramanian | 2016-11-22 |
| 9384016 | Method of estimating program speed-up with highly parallel architectures | Newsha Ardalani, Xiaojin Zhu | 2016-07-05 |
| 9384858 | Computer system predicting memory failure | Amir Yazdanbakhsh, Raghuraman Balasubramanian, Anthony Nowatzki | 2016-07-05 |
| 9298497 | Computer processor providing exception handling with reduced state storage | Jaikrishnan Menon, Marc Asher De Kruijf | 2016-03-29 |
| 9244772 | Computer processor providing error recovery with idempotent regions | Marc Asher De Kruijf, Chen-Han Ho | 2016-01-26 |
| 9231865 | Lookup engine with reconfigurable low latency computational tiles | Eric Harris, Samuel Lawrence Wasmundt | 2016-01-05 |
| 7940755 | Lookup engine with programmable memory topology | Cristian Estan | 2011-05-10 |
| 6772199 | Method and system for enhanced cache efficiency utilizing selective replacement exemption | Thomas Walter Keller | 2004-08-03 |