Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AT

Arun Thandapani — 9 Patents

WTWestern Digital Technologies: 5 patents #666 of 3,180Top 25%
STSandisk Technologies: 4 patents #929 of 2,594Top 40%
Bengaluru, IN: #799 of 15,622 inventorsTop 6%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Arun Thandapani has been granted 9 US patents while listed as an inventor at Western Digital Technologies. The first was granted in 2017 and the most recent in June 2023. Arun Thandapani ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Arun Thandapani in Bengaluru, IN.

Patents per Year

Patents granted per year, 2017 to 2023Bar chart with a peak of 2 patents in 2020.peak 22017: 1 patents20172018: 1 patents20182019: 1 patents20192020: 2 patents20202021: 2 patents20212022: 1 patents20222023: 1 patents2023

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11687409 Data storage device and method for data protection using XOR parity Varun Sharma, Vishal Sharma 2023-06-27 $9,761,000
11231883 Detecting last page written in multi-plane non-volatile memory Ankit Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Lee M. Gavens 2022-01-25 $12,540,000
11036407 Storage system and method for smart folding Rakshit Tikoo, Ankit Naghate, Yogendra Singh Sikarwar 2021-06-15 $29,617,000
11036411 Yield improvement through block budget optimization by using a transient pool of multi-level blocks Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Ramkumar Ramamurthy 2021-06-15 $29,617,000
10553301 Dynamic read table block filter Narayan K, Sateesh Desireddi, Aneesh Puthoor, Dharmaraju Marenahally Krishna, Divya Madapusi Srinivas Prasad +2 more 2020-02-04
10535383 Throughput performance for cross temperature handling scenarios Anantharaj Thalaimalaivanaraj, Suman Tenugu, Dharmaraju Marenahally Krishna, Sainath Viswasarai 2020-01-14
10319445 Programming unprogrammed upper page during lower page programming of multi-level storage cells Bhavadip Bipinbhai Solanki, Anantharaj Thalaimalai Vanaraj, Suman Tenugu, Piyush A. Dhotre, Chittoor Devarajan Sunilkumar +1 more 2019-06-11 $26,077,000
10073627 Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy 2018-09-11
9691485 Storage system and method for marginal write-abort detection using a memory parameter change Chittoor Devarajan Sunil Kumar, Divya Madapusi Srinivas Prasad, Piyush A. Dhotre, Dharmaraju Marenahally Krishna, Thendral Murugaiyan 2017-06-27