| 5668967 |
Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency |
Stephen W. Olson, Edward D. Mann, James W. Petersen, Jr. |
1997-09-16 |
| 5587673 |
Clock frequency multiplying and squaring circuit and method |
— |
1996-12-24 |
| 5479628 |
Virtual address translation hardware assist circuit and method |
Stephen W. Olson, Richard W. Lones |
1995-12-26 |
| 5475322 |
Clock frequency multiplying and squaring circuit and method |
— |
1995-12-12 |
| 5377338 |
Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency |
Stephen W. Olson, Edward D. Mann, James W. Petersen, Jr. |
1994-12-27 |
| 5123108 |
Improved CPU pipeline having register file bypass and working register bypass on update/access address compare |
Stephen W. Olson |
1992-06-16 |
| 5101478 |
I/O structure for information processing system |
Andrew N. Fu, Tom R. Kibler, Robert C. Nash, Stephen W. Olson, Bhikoo J. Patel +4 more |
1992-03-31 |
| 4747070 |
Reconfigurable memory system |
Robert R. Trottier, John Martins, Dennis J. Kayser |
1988-05-24 |