KG

Kumar Ganapathy

VS Virident Systems: 46 patents #3 of 20Top 15%
IN Intel: 26 patents #1,498 of 30,777Top 5%
CS Conexant Systems: 1 patents #311 of 657Top 50%
📍 Los Altos, CA: #103 of 3,651 inventorsTop 3%
🗺 California: #3,955 of 386,348 inventorsTop 2%
Overall (All Time): #26,510 of 4,157,543Top 1%
74
Patents All Time

Issued Patents All Time

Showing 51–74 of 74 patents

Patent #TitleCo-InventorsDate
7318115 IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic Ruban Kanapathippillai, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta +1 more 2008-01-08
7287148 Unified shared pipeline allowing deactivation of RISC/DSP units for power saving Ruban Kanapathippillai, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta +1 more 2007-10-23
7233166 Bus state keepers Ruban Kanapathippillai, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta +1 more 2007-06-19
7159169 Apparatus and methods for forward error correction decoding Hooman Honary, Amit Gupta, Siva Simanapalli 2007-01-02
7155541 Tables with direct memory access descriptor lists for distributed direct memory access Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah 2006-12-26
7062637 DSP operations with permutation of vector complex data type operands Ruban Kanapathipillai 2006-06-13
6988184 Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations Ruban Kanapathipillai 2006-01-17
6944087 Method and apparatus for off boundary memory access Ruban Kanapathippillai, Thu Nguyen 2005-09-13
6874039 Method and apparatus for distributed direct memory access for systems on chip Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah 2005-03-29
6842845 Methods and apparatuses for signal processing Ruban Kanapathipillai 2005-01-11
6842850 DSP data type matching for operation using multiple functional units Ruban Kanapathipillai 2005-01-11
6832306 Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions Ruban Kanapathipillai 2004-12-14
6772319 Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions Ruban Kanapathipillai 2004-08-03
6766446 Method and apparatus for loop buffering digital signal processing instructions Ruban Kanapathipillai, Kenneth Malich 2004-07-20
6748516 Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously Ruban Kanapathipillai 2004-06-08
6732203 Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus Ruban Kanapathippillai, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta +1 more 2004-05-04
6643768 Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder Ruban Kanapathipillai 2003-11-04
6631461 Dyadic DSP instructions for digital signal processors Ruban Kanapathipillai 2003-10-07
6598155 Method and apparatus for loop buffering digital signal processing instructions Ruban Kanapathipillai, Kenneth Malich 2003-07-22
6557096 Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types Ruban Kanapathipillai 2003-04-29
6446195 Dyadic operations instruction processor with configurable functional blocks Ruban Kanapathipillai 2002-09-03
6442672 Method for dynamic allocation and efficient sharing of functional unit datapaths 2002-08-27
6408376 Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously Ruban Kanapathipillai 2002-06-18
6330660 Method and apparatus for saturated multiplication and accumulation in an application specific signal processor Ruban Kanapathipillai 2001-12-11