Issued Patents All Time
Showing 251–275 of 277 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5517671 | System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus | Darius D. Gaskins | 1996-05-14 |
| 5515305 | PDA having chord keyboard input device and method of providing data thereto | David S. Register | 1996-05-07 |
| 5483641 | System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities | Craig S. Jones, Kenneth L. Jeffries | 1996-01-09 |
| 5483260 | Method and apparatus for simplified video monitor control | Joseph Bell | 1996-01-09 |
| 5477237 | Positioning device reporting X, Y and yaw motion | — | 1995-12-19 |
| 5477551 | Apparatus and method for optimal error correcting code to parity conversion | Darius D. Gaskins | 1995-12-19 |
| 5473761 | Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests | Kenneth L. Jeffries, Craig S. Jones | 1995-12-05 |
| 5471225 | Liquid crystal display with integrated frame buffer | — | 1995-11-28 |
| 5469559 | Method and apparatus for refreshing a selected portion of a dynamic random access memory | David S. Register | 1995-11-21 |
| 5465346 | Method and apparatus for synchronous bus interface optimization | Darius D. Gaskins | 1995-11-07 |
| 5463643 | Redundant memory channel array configuration with data striping and error correction capabilities | Darius D. Gaskins | 1995-10-31 |
| 5455466 | Inductive coupling system for power and data transfer | David S. Register | 1995-10-03 |
| 5452463 | Processor and cache controller interface lock jumper | Thomas Holman | 1995-09-19 |
| 5448697 | Method and apparatus for simplified control of a video monitor | Joseph Bell | 1995-09-05 |
| 5432735 | Ternary storage dynamic RAM | Darius D. Gaskins | 1995-07-11 |
| 5404454 | Method for interleaving computer disk data input-out transfers with permuted buffer addressing | — | 1995-04-04 |
| 5384788 | Apparatus and method for optimal error correcting code to parity conversion | Darius D. Gaskins | 1995-01-24 |
| 5369605 | Incremental search content addressable memory for increased data compression efficiency | — | 1994-11-29 |
| 5359611 | Method and apparatus for reducing partial write latency in redundant disk arrays | E. Alan Davis, Geoffrey B. Hoese | 1994-10-25 |
| 5357622 | Apparatus for queing and storing data writes into valid word patterns | Darius D. Gaskins, Michael L. Longwell, Keith D. Matteson | 1994-10-18 |
| 5355251 | Liquid crystal display device with octagonal cell providing increased wiring density | — | 1994-10-11 |
| 5325508 | Processor that performs memory access in parallel with cache access | Keith D. Matteson | 1994-06-28 |
| 5261068 | Dual path memory retrieval system for an interleaved dynamic RAM memory unit | Darius D. Gaskins, Thomas Holman, Michael L. Longwell, Keith D. Matteson | 1993-11-09 |
| 5239445 | Method and apparatus for simultaneous operation of two IDE disk drives | Joseph M. Maurin, Kenneth L. Jeffries | 1993-08-24 |
| 5163145 | Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference | — | 1992-11-10 |