JN

Joseph Nee

VT Via Technologies: 2 patents #343 of 1,108Top 35%
Overall (All Time): #2,170,241 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7064445 Wafer level testing and bumping process Yu-Lung Yu 2006-06-20
6869809 Wafer level testing and bumping process Yu-Lung Yu 2005-03-22