JL

James R. Lundberg

VT Via Technologies: 50 patents #8 of 1,108Top 1%
IP Ip-First: 14 patents #5 of 27Top 20%
Motorola: 10 patents #938 of 12,470Top 8%
DE Digital Equipment: 4 patents #305 of 2,100Top 15%
VC Via Alliance Semiconductor Co.: 3 patents #38 of 157Top 25%
IT Integrated Device Technology: 2 patents #282 of 758Top 40%
IL I.P.-First, L.L.C.: 1 patents #8 of 11Top 75%
II Intermec Ip: 1 patents #211 of 391Top 55%
CT Centaur Technology: 1 patents #8 of 16Top 50%
🗺 Texas: #566 of 125,132 inventorsTop 1%
Overall (All Time): #18,860 of 4,157,543Top 1%
88
Patents All Time

Issued Patents All Time

Showing 26–50 of 88 patents

Patent #TitleCo-InventorsDate
8751850 Optimized synchronous data reception mechanism Darius D. Gaskins 2014-06-10
8683253 Optimized synchronous strobe transmission mechanism Darius D. Gaskins 2014-03-25
8242802 Location-based bus termination for multi-core processors Darius D. Gaskins 2012-08-14
8179178 Registers with reduced voltage clocks 2012-05-15
8085062 Configurable bus termination for multi-core/multi-package processor configurations Darius D. Gaskins 2011-12-27
7990180 Fast dynamic register Imran Qureshi 2011-08-02
7978001 Microprocessor with selective substrate biasing for clock-gated functional blocks Raymond A. Bertram, Mark J. Brazell, Vanessa S. Canac, Darius D. Gaskins, Matthew Russell Nixon 2011-07-12
7920019 Microprocessor with substrate bias clamps Raymond A. Bertram, Mark J. Brazell, Vanessa S. Canac, Darius D. Gaskins, Matthew Russell Nixon 2011-04-05
7900080 Receiver mechanism for source synchronous strobe lockout 2011-03-01
7900129 Encoded mechanism for source synchronous strobe lockout Darius D. Gaskins 2011-03-01
7899143 Adjustment mechanism for source synchronous strobe lockout 2011-03-01
7843225 Protocol-based bus termination for multi-core processors Darius D. Gaskins 2010-11-30
7812662 System and method for adjusting supply voltage levels to reduce sub-threshold leakage 2010-10-12
7804923 Apparatus and method for locking out a source synchronous strobe receiver 2010-09-28
7767492 Location-based bus termination for multi-core/multi-package processor configurations Darius D. Gaskins 2010-08-03
7543090 Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout 2009-06-02
7417465 N-domino output latch Raymond A. Bertram 2008-08-26
7411840 Sense mechanism for microprocessor bus inversion Darius D. Gaskins 2008-08-12
7382161 Accelerated P-channel dynamic register Raymond A. Bertram 2008-06-03
7358758 Apparatus and method for enabling a multi-processor environment on a bus Darius D. Gaskins 2008-04-15
7348806 Accelerated N-channel dynamic register Raymond A. Bertram 2008-03-25
7288980 Multiple mode clock receiver 2007-10-30
7278040 Mechanism for providing measured power management transitions in a microprocessor Darius D. Gaskins 2007-10-02
7271679 Apparatus and method to facilitate wireless communications of automatic data collection devices in potentially hazardous environments Robert A. Zigler, For Sander Lam 2007-09-18
7212039 Dynamic logic register Imran Qureshi 2007-05-01