Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12273200 | Methods and devices for transmitting and receiving non-binary error correcting code words | Valentin Savin | 2025-04-08 |
| 11545998 | Offset value determination in a check node processing unit for message-passing decoding of non-binary codes | Hassan Harb, Cédric Marchand | 2023-01-03 |
| 11476870 | Variable node processing methods and devices for message-passing decoding of non-binary codes | Cédric Marchand, Hassan Harb | 2022-10-18 |
| 11290128 | Simplified check node processing in non-binary LDPC decoder | Cédric Marchand | 2022-03-29 |
| 11245421 | Check node processing methods and devices with insertion sort | Cédric Marchand, Hassan Harb | 2022-02-08 |
| 11133827 | Simplified, presorted, syndrome-based, extended min-sum (EMS) decoding of non-binary LDPC codes | Cédric Marchand | 2021-09-28 |
| 11095308 | Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes | Cédric Marchand | 2021-08-17 |
| 10637510 | Methods and devices for error correcting codes decoding | Cédric Marchand | 2020-04-28 |
| 10560120 | Elementary check node processing for syndrome computation for non-binary LDPC codes decoding | Cédric Marchand | 2020-02-11 |
| 10554226 | Method for controlling a check node of a NB-LDPC decoder and corresponding check node | Philipp Schläfer, Timo Lehnigk-Emden | 2020-02-04 |
| 10476523 | Elementary check node-based syndrome decoding using pre-sorted inputs | Cédric Marchand | 2019-11-12 |
| 10432224 | Methods and devices for generating optimized coded modulations | Ahmed Abdmouleh | 2019-10-01 |
| 10361723 | Decoding of non-binary LDPC codes | Oussama Abassi, Laura Conde-Canencia | 2019-07-23 |
| 10298262 | Decoding low-density parity-check maximum-likelihood single-bit messages | Chris Winstead | 2019-05-21 |
| 9843414 | Low complexity error correction | Chris Winstead, Gopalakrishnan Sundararajan | 2017-12-12 |
| 9438305 | Method for transmitting non binary error correcting code words with CCSK modulation, and corresponding signal and device | Laura Conde-Canencia, Oussama Abassi | 2016-09-06 |
| 8645787 | Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor | Laura Conde-Canencia | 2014-02-04 |
| 7472359 | Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams | Maciej Ciesielski, Serkan Askar, Jeremie Guillot | 2008-12-30 |
| 7174495 | LDPC decoder, corresponding method, system and computer program | Jacky Tousch, Frederic Guilloud | 2007-02-06 |
| 5335195 | Method and circuit for processing digital signals representative of vectors or tuples of the same dimension and application thereof to sets having any cardinality and to vectors or tuples of any dimensions | Francis Jutand, Anne Lafage | 1994-08-02 |