Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11417413 | Semiconductor memory apparatus and method for reading the same | — | 2022-08-16 |
| 11270751 | Pseudo static random access memory and method for writing data thereof | — | 2022-03-08 |
| 11010243 | Memory apparatus with error bit correction in data reading period | — | 2021-05-18 |
| 11004533 | Memory device and built-in self test method thereof | — | 2021-05-11 |
| 10891990 | Memory device | — | 2021-01-12 |
| 10872651 | Volatile memory device and self-refresh method by enabling a voltage boost signal | — | 2020-12-22 |
| 10825546 | Memory device and memory peripheral circuit | — | 2020-11-03 |
| 10770118 | Reverse bias voltage adjuster | — | 2020-09-08 |
| 10679692 | Memory apparatus and majority detector thereof | — | 2020-06-09 |
| 10665316 | Memory device | — | 2020-05-26 |
| 10607679 | Memory device and refreshing method thereof | — | 2020-03-31 |
| 10586576 | Memory device | — | 2020-03-10 |
| 10566034 | Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels | — | 2020-02-18 |
| 10424362 | Memory device and data refreshing method thereof | — | 2019-09-24 |
| 10395720 | Pseudo static random access memory and refresh method thereof | — | 2019-08-27 |
| 10255954 | Memory device | — | 2019-04-09 |
| 9208831 | Semiconductor memory device | Keisuke Nomoto | 2015-12-08 |
| 8861299 | Semiconductor memory device | Keisuke Nomoto | 2014-10-14 |
| 8570815 | Semiconductor device and method of controlling the same | — | 2013-10-29 |
| 8355270 | Semiconductor device having open bit line architecture | Hiroshi Ichikawa | 2013-01-15 |
| 8295113 | Semiconductor device | — | 2012-10-23 |
| RE36621 | Semiconductor memory device | — | 2000-03-21 |
| 6038648 | Semiconductor memory device having the same access timing over clock cycles | — | 2000-03-14 |
| 6021077 | Semiconductor memory device controlled in synchronous with external clock | — | 2000-02-01 |
| 5864510 | Semiconductor memory device having a bit compressed test mode and a check mode selecting section | — | 1999-01-26 |